1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate structures including a high-k gate dielectric material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers in the channel region.
The continuous shrinkage of critical dimensions of transistor elements has resulted in a gate length of field effect transistors of 50 nm and significantly less, thereby providing sophisticated semiconductor devices having enhanced performance and an increased packing density. The increase of electrical performance of the transistors is strongly correlated with a reduction of the channel length, which may result in an increased drive current and switching speed of the field effect transistors. On the other hand, the reduction of the channel length is associated with a plurality of issues in terms of channel controllability and static leakage currents of these transistors. It is well known that field effect transistors with a very short channel may require an increased capacitive coupling between the gate electrode structure and the channel region in order to provide the desired static and dynamic current flow controllability. Typically, the capacitive coupling is increased by reducing the thickness of the gate dielectric material, which is typically formed on the basis of a silicon dioxide base material, possibly in combination with a nitrogen species, due to the superior characteristics of a silicon/silicon dioxide interface. Upon implementing a channel length of the above-identified order of magnitude, however, the thickness of the silicon dioxide based gate dielectric material may reach values of 1.5 nm and less, which in turn may result in significant leakage currents due to a direct tunneling of the charge carriers through the very thin gate dielectric material. Since the exponential increase of the leakage currents upon further reducing the thickness of silicon dioxide based gate dielectric materials is not compatible with the thermal power design requirements, other mechanisms have been developed so as to further enhance transistor performance and/or reduce the overall transistor dimensions.
For example, by creating a certain strain component in the channel region of silicon-based transistor elements, the charge carrier mobility and, thus, the overall conductivity of the channel may be enhanced. For a silicon material with a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, tensile strain in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain in the current flow direction may increase the mobility of holes and may, thus, provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past, wherein internal strain-inducing sources, such as an embedded strain-inducing semiconductor material, have proven to be very efficient strain-inducing mechanisms. For example, frequently, the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors is applied in order to enhance performance of these transistors. For this purpose, in an early manufacturing stage, cavities are formed in the active region laterally adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer and a resist mask. These cavities may be subsequently refilled with the silicon/germanium alloy on the basis of selective epitaxial growth techniques. During the etch process for forming the cavities and during the subsequent epitaxial growth process, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose sensitive materials of the gate electrode structure, such as a silicon-based electrode material, to the process ambient for forming the cavities and for selectively growing the silicon/germanium alloy. Thereafter, the gate electrode structures may be exposed and the further processing may be continued by forming drain and source regions in accordance with any appropriate process strategy.
Basically, the above-described strain-inducing mechanism is a very efficient concept for improving transistor performance of P-channel transistors, wherein the efficiency of the finally obtained strain in the channel region of the transistor, however, strongly depends on the internal strain level of the semiconductor alloy and on the lateral offset of this material from the channel region. Typically, the material composition of the strain-inducing semiconductor alloy is restricted by currently available sophisticated selective epitaxial deposition recipes, which, in the case of a silicon/germanium alloy, may presently not allow germanium concentrations of significantly more than approximately 30 atomic percent. Consequently, a further improvement of the total strain in the channel region requires a reduction of the lateral offset of the silicon/germanium alloy from the channel region so that any protective spacer structures may have to be provided with a reduced width.
In addition to providing strain-inducing mechanisms in sophisticated field effect transistors, also sophisticated gate electrode materials have been proposed in order to overcome the restrictions of conventional silicon dioxide/polysilicon based gate electrode structures. To this end, the conventional silicon dioxide based gate dielectric material is replaced, at least partially, by a so-called high-k dielectric material, i.e., a dielectric material having a dielectric constant of 10.0 and higher, which may result in a desired high capacitance between the gate electrode and the channel region, while nevertheless a certain minimum physical thickness is provided so as to keep the resulting leakage currents at an acceptable level. For this purpose, a plurality of dielectric materials, such as hafnium oxide based materials, zirconium oxide, aluminum oxide and the like, are available and may be used in sophisticated gate electrode structures. Furthermore, the polysilicon material may also be replaced, at least in the vicinity of the gate dielectric material, since typically polysilicon suffers from charge carrier depletion in the vicinity of the gate dielectric material, which may reduce the effective capacitance. Moreover, with sophisticated high-k gate dielectric materials, the work function of standard polysilicon materials obtained by a corresponding doping may no longer be sufficient to provide the required electronic characteristics of the gate electrode material in order to obtain a desired threshold voltage of the transistors under consideration. For this reason, specific work function adjusting metal species, such as aluminum, lanthanum and the like, are typically incorporated in the gate dielectric material and/or in an appropriate electrode material in order to obtain a desired work function and also increase conductivity of the gate electrode material at least in the vicinity of the gate dielectric material.
Thus, a plurality of sophisticated process strategies have been developed, wherein, in some promising approaches, the sophisticated gate materials, such as a high-k dielectric material and a metal-containing electrode material, possibly including a work function adjusting metal species, may be provided in an early manufacturing stage in combination with a polysilicon material, thereby providing a high degree of compatibility with conventional process strategies for forming sophisticated field effect transistors. It turns out, however, that a reliable confinement of the sensitive material system, including the high-k dielectric material and the metal-containing electrode material, has to be guaranteed in order to avoid a shift in threshold voltage or any other variabilities of the sophisticated high-k metal gate electrode structures.
In an attempt to further enhance device performance of sophisticated field effect transistors, it has been proposed to combine sophisticated high-k metal gate electrode structures with a strain-inducing mechanism, for instance, by incorporating a strain-inducing semiconductor alloy in the active regions of the transistors. In this case, the encapsulation of the gate electrode structure of the transistor, which may require the incorporation of an embedded strain-inducing semiconductor alloy, may have to be implemented on the basis of detrimental requirements. On the one hand, the confinement of the gate electrode structure has to ensure integrity of the sensitive material system, for example, prior to, during and after the incorporation of the strain-inducing semiconductor material, and, on the other hand, a reduced thickness of any protective spacer elements, such as silicon nitride based materials, is to be implemented in view of enhancing efficiency of the strain-inducing mechanism. Consequently, a compromise of thickness of the spacer elements and gain in performance of sophisticated transistors is typically applied.
Consequently, in sophisticated process strategies in which the sophisticated metal gate electrode structures are formed in an early manufacturing stage, reliable confinement of the sensitive gate materials is mandatory in order to not unduly compromise overall production yield. It has been observed, however, that significant gate failures may occur, in particular in the gate electrode structures of N-channel transistors, as will be described in more detail with reference to FIGS. 1a-1h. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 in which a gate layer stack 160s is formed above active regions 102a, 102b, 102c and an isolation region (not shown), wherein a part of the gate layer stack 160s is already patterned to a certain degree, thereby providing substantially stripe-like hard mask layers 164.
It should be appreciated that, for convenience, the active regions 102a, 102b, 102c are visible, although these regions are actually covered by the gate layer stack 160s, which may be described in more detail with reference to the following figures. In the example shown, the active region 102a corresponds to a semiconductor region in and above which P-channel transistors are to be formed, while the active regions 102b, 102c represent the semiconductor regions of N-channel transistors. Furthermore, as illustrated, the hard mask layers 164, which may be comprised of any appropriate material system, such as silicon dioxide, silicon nitride and the like, are patterned so as to substantially implement a desired gate length, as indicated by 1601, while the patterning of the hard mask material 164 in a direction along a width direction W is to be accomplished in a later manufacturing stage. That is, in this stage, the hard mask layers 164 substantially define the lateral dimension of the gate electrode structures still to be formed from the gate layer stack 160s along a gate length direction, as indicated by the gate length 1601, while an appropriate patterning along the width direction W has to be performed on the basis of an additional lithography and patterning process sequence in order to adjust a desired lateral distance 160d of neighboring gate electrode structures that are aligned to each other along the width direction.
FIG. 1b schematically illustrates a top view of the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the hard mask layers 164 are now also patterned so as to implement the desired lateral dimension of gate electrode structures still to be formed along the width direction W, thereby determining the lateral distance 160d in accordance with the basic design rules. It should be appreciated that the distance 160d provides for a separation of corresponding gate electrode structures along the width direction in order to ensure electrical insulation of individual gate electrode structures, when required by the overall circuit layout. The patterning of the hard mask material 164 is typically accomplished by using an additional mask material and patterning the same so as to provide a trench therein, which is appropriately dimensioned in order to obtain the distance 160d upon patterning the underlying hard mask material 164 on the basis of the additional mask material.
FIG. 1c schematically illustrates a cross-sectional view of the semiconductor device 100 according to the section as indicated by Ic in FIG. 1b. As shown, the semiconductor device 100 comprises a substrate 101, such as a silicon material or any other appropriate carrier material for forming thereabove a semiconductor layer 102, such as a silicon layer or any other appropriate semiconductor material which comprises a significant amount of silicon. The semiconductor layer 102 is divided into the various active regions by means of an isolation region 103, which in turn is comprised of appropriate dielectric materials, such as silicon dioxide, silicon nitride and the like. In the sectional view of FIG. 1c, the active regions 102a, 102b are illustrated, wherein the active region 102a comprises a threshold voltage adjusting semiconductor alloy 104, for instance in the form of a silicon/germanium alloy. As previously discussed, the semiconductor material 104 is typically required for appropriately adjusting the threshold voltage offset between P-channel transistors and N-channel transistors for a given complex configuration of a gate electrode structure still to be formed for these transistors. Furthermore, the gate layer stack 160s is illustrated so as to comprise a layer system 161, which includes at least a high-k dielectric material, typically in combination with an additional very thin conventional dielectric material, thereby enhancing the overall interface characteristics between the layer system 161 and the active region 102a comprising the alloy 104 and the active region 102b. Furthermore, frequently, the layer system 161 comprises an electrode material, for instance in the form of titanium nitride, tantalum nitride and the like, wherein also appropriate metal species may be incorporated so as to obtain a desired work function for the gate electrode structures still to be formed. It should be appreciated that any such work function adjusting metal species may be selected differently for P-channel transistors and N-channel transistors. For example, materials such as aluminum, lanthanum and the like may be used in a corresponding electrode material and/or within the dielectric material of the layer system 161, wherein appropriate metal species may be diffused into the dielectric material on the basis of appropriately selected anneal processes upon forming the layer system 161. In this case, the basic electronic characteristics of the P-channel transistors to be formed in and above the active region 102a and the N-channel transistors to be formed in and above the active region 102b may be adjusted in an early manufacturing stage, i.e., prior to actually patterning the gate electrode structures and completing the overall transistor configurations. Furthermore, the gate layer stack 160s may comprise an additional electrode material 162, such as a silicon material and the like, followed by the hard mask layer system 164 which, in this manufacturing stage, is already patterned in one lateral direction so as to substantially determine the gate length 1601 of gate electrode structures still to be formed.
The semiconductor device 100 as shown in FIG. 1c may be formed on the basis of the following processes. The isolation region 103 is typically formed on the basis of sophisticated lithography, etch, deposition, anneal and planarization techniques, wherein the lateral size and shape of the isolation region 103 is appropriately selected so as to define the lateral size and shape of the active regions in the layer 102. Prior to or after forming the isolation region 103, the basic dopant concentration in the corresponding active regions is implemented, for instance, by performing implantation processes in combination with appropriate masking steps. Next, an appropriate hard mask is formed so as to selectively cover the active regions of transistors which do not require the threshold voltage adjusting semiconductor material 104. In FIGS. 1a, 1b and 1c, these active regions may correspond to the active regions 102b, 102c. To this end, any appropriate hard mask material, such as silicon dioxide, is formed and is selectively removed from the active region 102a, while other active regions are covered by an appropriate mask. Thereafter, the exposed active region 102a may be prepared for a subsequent selective epitaxial growth process in order to form the material 104. During the patterning of the corresponding hard mask material and also during any further cleaning steps for preparing the active region 102a, a significant degree of recessing 103r may be generated in the isolation structure 103 in the vicinity of the active region 102a, which may have a significant influence on the further processing. Thereafter, the gate layer stack 160s is formed, for instance, by first providing the material system 161, which may include a plurality of deposition and patterning processes in order to form a high-k dielectric material in combination with appropriate work function metal species and an appropriate electrode material, as discussed above. To this end, well-established process recipes are available. For convenience, individual metal layers of the system 161 as well as the difference in electronic characteristics, such as work function and the like, are not shown in FIG. 1c. Next, the electrode material 162 is deposited in combination with the hard mask system 164, which is accomplished on the basis of well-established deposition techniques. Next, the hard mask material 164 is patterned so as to form the corresponding stripe-like configuration as shown in FIG. 1a, thereby basically defining the gate length 1601. To this end, an appropriate mask may be formed, for instance on the basis of resist, which may be patterned by using sophisticated lithography techniques, followed by appropriate resist trim processes, as are well established in the art. Thereafter, an etch process is performed in order to etch through the layer 164.
Thereafter, further mask material (not shown) may be deposited and may be patterned so as to form an appropriate mask opening, which basically defines the lateral distance 160d (FIG. 1a), which may be accomplished by using a further lithography and etch sequence in order to pattern the hard mask materials 164 for determining a lateral size of these materials along the width direction, i.e., in FIG. 1c, the direction perpendicular to the drawing plane, as is also illustrated in FIG. 1b, thereby actually implementing the lateral distance 160d. Thereafter, the additional mask material is removed and the patterned hard mask material 164 is used for patterning the remaining layers of the gate layer stack 160s on the basis of sophisticated patterning techniques.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, i.e., in a manufacturing stage in which gate electrode structures 160a, 160b are patterned and formed above the active regions 102a, 102b, respectively. Hence, the gate electrode structures 160a, 160b comprise the material system 161 followed by the electrode material 162 and a dielectric cap layer system, which represents the remaining portion of the hard mask material 164. Consequently, the gate electrode structures 160a, 160b are provided with a desired complex configuration including a high-k dielectric material in the system 161 and having appropriate lateral dimensions, such as a desired gate length 1601 (FIG. 1c). Moreover, as discussed above, P-channel transistors to be formed in and above the active region 102a have to be implemented on the basis of an embedded strain-inducing silicon/germanium alloy in order to further enhance performance of the device 100. Furthermore, as also discussed above, in particular the sensitive materials in the system 161 have to be confined in order to avoid undue contact with aggressive chemicals, as are typically required for performing efficient cleaning processes, for instance by using well-established cleaning agents, such as SPM (sulfuric acid/hydrogen peroxide mixture) and the like. Consequently, a protective liner or spacer is to be formed on sidewalls of the gate electrode structures 160a, 160b, which also may define the lateral offset of a strain-inducing semiconductor material to be formed selectively in the active region 102a. To this end, an appropriate dielectric material, such as silicon nitride, is typically deposited in a highly conformal manner with a desired high material density in order to provide a moderately thin yet highly robust material layer, thereby attempting to ensure reliable confinement of the material system 161 and also provide a desired reduced lateral offset of the strain-inducing material to be formed in the active region 102a. 
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a spacer layer 163 is formed in a conformal manner above the active regions 102a, 102b, the isolation region 103 and above the gate electrode structures 160a, 160b. The thickness and material composition of the spacer layer 163 is selected so as to basically meet the above-addressed requirements with respect to confinement of sensitive material and providing a reduced lateral offset. To this end, a plurality of well-established deposition techniques, such as multi-layer deposition, low pressure chemical vapor deposition (CVD) and the like, are available. Thereafter, a resist mask 105 is formed so as to cover the gate electrode structure 160b and the active region 102b, in which the strain-inducing semiconductor material is not to be formed. Due to the very pronounced surface topography of the isolation region 103 in the vicinity of the active region 102a, however, the exposure and patterning process for forming the resist mask 105 may suffer from topography-related irregularities, thereby forming a pronounced resist foot, as indicated by 105f, at the foot or lower portion of the resist mask 105, which in turn may significantly affect the further processing of the device 100 upon patterning the spacer layer 163 and forming recesses in the active region 102a. 
FIG. 1f schematically illustrates a cross-sectional view of the semiconductor device 100 in a sectional view as indicated by the line If in FIG. 1b. As shown, in this section, the isolation region 103 laterally separates the active region 102a from the active region 102c and also comprises a significant recess in the vicinity of the active region 102a. Moreover, a gate electrode structure 160c is formed above the active region 102c and extends above the isolation region 103. As also explained above with reference to FIGS. 1a and 1b, the gate electrode structures 160a, 160c are thus separated substantially by the lateral distance 160d, which ensures electrical isolation of the gate electrode structures 160a, 160c while still ensuring that the gate electrode structures 160a, 160c completely span the corresponding active regions 102a, 102c, respectively. Furthermore, as shown, the resist mask 105 is formed so as to cover the active region 102c and the gate electrode structure 160c since the incorporation of a strain-inducing semiconductor material is not required in the active region 102c, as discussed above. Due to the pronounced footing of the resist mask 105, as explained above, and due to the fact that the undue lateral dimensions of the mask 105 at the foot of the gate electrode structures may not be acceptable for the further processing, a further resist etch process 106 is applied in order to reduce the lateral dimensions of the resist mask 105 at the lower portions of the gate electrode structures. For example, typically, an oxygen-based plasma etch process with short exposure time may be applied, wherein, however, a significant material erosion has to be induced so as to remove unwanted resist material portions. On the other hand, generally material erosion is induced in the mask 105, thereby resulting in a reduced resist mask 105r which, however, may even expose an end portion 160e of the gate electrode structure 160c so that, in particular, the spacer layer 163 at the end portion 160e may be exposed during the further processing.
FIG. 1g schematically illustrates the semiconductor device 100 in a manufacturing stage in which an etch sequence 115 is performed in the presence of the reduced resist mask 105r so that sidewall spacers 163s are formed from an exposed portion of the spacer layer 163 during a first phase of the etch sequence 115. Furthermore, typically, the etch sequence 115 is continued so as to etch into the active region 102a, while using the cap material 164, the spacers 163s and the resist mask 105r as an etch mask. Consequently, during the further processing, cavities 114 may be formed in the active region 102a, wherein the lateral offset of the cavities 114 with respect to a channel region 153 is substantially determined by the spacer 163s. 
Again referring to FIG. 1f, during the process 115 as shown in FIG. 1g, the material of the spacer layer 163 in the end portion 160e may be exposed to the plasma etch ambient, thereby contributing to a certain degree of material erosion and thus also forming a spacer portion at the end portion 160e of the gate electrode structure 160c. 
FIG. 1h schematically illustrates the semiconductor device 100 in a cross-sectional view according to the section as indicated as Ic in FIG. 1b. As shown, a strain-inducing semiconductor material 151, for example in the form of a silicon/germanium alloy and the like, is formed in the cavities 114, which may be accomplished by applying selective epitaxial growth techniques, wherein, after the removal of the resist mask 105r (FIG. 1g), the layer 163 (FIG. 1g) acts as a deposition mask for any active regions and gate electrode structures in which the incorporation of the strain-inducing semiconductor material 151 is not required. After the selective growth of the material 151, a further resist mask 108 may be provided so as to cover the active region 102a and the gate electrode structure 160a, while exposing the gate electrode structure 160b. On the basis of the resist mask 108, a further etch process 107 may be applied so as to form the spacers 163s on the gate electrode structure 160b from the remaining spacer layer 163 (FIG. 1g). During the etch process 107, however, the end portion of the gate electrode structure 160c (FIG. 1f) is again exposed to a reactive etch ambient and thus suffers again from a certain degree of material erosion, for instance contrary to the gate electrode structure 160a in which the spacers 163s are formed during the etch sequence 115 (FIG. 1g), while the material 163s, however, is reliably covered by the mask 108 during the process 107. Hence, the end portion of the gate electrode structures 160b, 160c (FIG. 1f) may thus be eroded in a more pronounced manner, which may finally result in a less reliable confinement of sensitive gate materials since typically, as discussed above, the width of the spacers 163s is selected so as to enable a reduced lateral offset of the material 151 in the active region 102a. Hence, increasing the width of the spacers 163s is less than desirable in view of sacrificing significant gain in transistor performance of P-channel transistors formed in and above the active region 102a. On the other hand, with respect to the process strategy as described above, an increased probability exists for exposing sensitive gate materials to highly aggressive chemicals, such as cleaning agents, thereby contributing to a significant material erosion of these sensitive materials, which in turn results in pronounced gate failures.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.